This invention relates generally to clock switching circuits and more particularly relates to a circuit to perform glitch-free selection of one clock signal from multiple clock signals.
The present day integrated circuits are highly complex, typically containing disparate pieces of circuits, such as millions of gates of logic and memory with different capabilities and characteristics. These circuits are, in general, synchronous circuits that is their operation is coordinated by master signals called clocks.
Some integrated circuits have to operate using multiple clocks. The frequencies of different clocks may or may not be integral multiples of one another. In addition, current circuits may have multiple modes of operation that could result in different rates of operation. For example, a circuit may have a high-frequency mode whenever it is necessary to process data at a faster rate and a low-frequency mode whenever it is necessary to reduce power dissipation. Such different modes of operation require different clocks operating at different frequencies. Yet another situation where a circuit may have to operate with multiple clocks, having unrelated frequencies, is when a circuit needs to be tested. Since external testers are typically slower than the circuits that are being tested, during testing the circuit may be supplied with a clock that is much slower than the regular system clock. In all these scenarios it is necessary to reliably select one of the multiple synchronous or asynchronous clock signals as the system clock.
Whenever the system clock needs to be switched to a different clock, this switching must be performed in a glitch-free manner, by avoiding pulses of width less than that determined by the fastest clock. Another concern when switching between multiple clocks is the possibility of metastability. The clock selection/switch circuit should provide means to reduce the probability of metastability.
There has been a lot of work in the area of clock selection/switching circuits. However, a majority of this work is limited to two clocks only. There are some references that describe circuits that are not limited to two clocks, but these circuits are overly complex. References U.S. Pat. Nos. 4,853,616, 4,970,405, and 6,107,841 are capable of handling multiple clocks and are less complex. However, U.S. Pat. Nos. 4,853,616 and 6,107,841 utilize one-hot encoded select signals to select one clock among multiple clocks. That is, each clock signal has a corresponding select signal that when high results in the selection of the corresponding clock signal. One-hot encoding for select signals implies that as the number of clocks increases so does the number of select signals, i.e., N clock signals will require N select lines. In addition, if the one-hot encoding is not strictly enforced (i.e., if more than one select signal is at a high state), then the output clock will be a combination of all the selected clocks. Such a clock can have arbitrary waveform and can easily corrupt the system.
In addition, reference U.S. Pat. No. 6,107,841 relies on a special signal to indicate when to switch the clocks. This signal, which is driven high after setting proper values on the select lines, needs to be in this high state for a very precise amount of time. Otherwise, the clock selector circuit will try to switch the current clock with itself, resulting in unnecessary dead cycles.
Reference U.S. Pat. No. 4,970,405 utilizes binary encoded select signals, resulting in ceil(log2N) select signals for N clock signals. However, it does not eliminate the possibility of glitches on the output clock. This is because the select lines pass through several levels of combinational logic before being gated with the clocks. Depending on the relative delays of the clock and select signals, there is a possibility of occurrence of glitches on the output clock. Glitches or pulses that are less than those determined by the fastest clock can corrupt the circuit.
Thus, it is desirable to provide a circuit that is capable of switching between multiple clocks while reducing or eliminating glitches and metastability. Furthermore it is desirable to not limit the encoding of clock selection signals to any particular style.
The proposed invention has the ability to reduce or eliminate glitches and metastability while selecting one clock from multiple asynchronous and/or synchronous clocks.
In one aspect, a circuit or block for determining the stability of the input select signals (xe2x80x9cthe stable selects blockxe2x80x9d) monitors the input select signals and activates a selects stable signal that indicates the select signals have been stable for at least a predetermined number of clock cycles. For as long as it is determined that the select signals are unstable, the selects stable signal is deactivated to signify that the select signals are not ready yet.
In another aspect, a circuit or block for decoding and propagating only select signals that are stable, (xe2x80x9cthe stable decoder blockxe2x80x9d) takes select signals as well as the selects stable signal from the stable select block. This decoder block decodes the select signals, and depending on the selects stable signal, passes on either these newly decoded select signals or the previously decoded select signals. As long as the selects stable signal is deactivated, the decoder re-circulates the previously decoded select signals. The exact configuration of the decoder block depends on the type of encoding scheme used for the input select signals. For example, the stable decoder block could include logic gates, such as AND, OR, and inverter gates for binary encoding, one-hot encoding, etc.
In another possible aspect, a circuit or block for synchronizing the decoded select signals to their corresponding clocks (xe2x80x9cthe synchronous selects blockxe2x80x9d) takes as input, the decoder output select signals and generates select signals that are in synchrony with their respective clocks. These are then supplied to a circuit or block for selecting and outputting the correct selected clock (xe2x80x9cthe output blockxe2x80x9d), which in one possible embodiment, combines (such as by using AND gates) the synchronous selects, their corresponding decoded select signals, and clocks. The outputs of the AND gates are then combined with an OR gate to obtain the final system or output clock. One skilled in the art would know that equivalent logic gates, combinations of gates, or other logic could easily be designed and used instead.
It is noteworthy that the present invention achieves glitch-free clock switching because of several features. First, there is a mechanism in the proposed invention to identify changes on the input select signals and ignore their values until they become stable. In the outlined embodiment the stable selects block produces a signal to indicate to the stable decoder block when the new select signals are ready to be used. This occurs only when the select signals are stable for at least a predetermined number of system clock cycles, thus eliminating multiple clock switches that can happen, due to race conditions, when more than one select signal changes. Yet another possible feature that contributes to the glitch-free clock switch is the fact that the decoded select signals and the synchronous select signals are fed directly to the output block. That is, these signals do not have to propagate through any combinational logic to reach the output block. This has the beneficial effect of eliminating the possibility of glitches on the output clock. In addition, the probability of metastability can be reduced to close to being insignificant by the use of serially coupled memory devices (xe2x80x9cstagesxe2x80x9d), such as flip-flops, in the stable selects block and the synchronous selects block. By increasing the number of flip-flop stages in the stable selects block and the synchronous selects block the probability of metastability can be rendered virtually inconsequential. However, the trade-off with increasing the number of flip-flop stages in these blocks is that it will increase the time required to switch clocks.
Further features and advantages will become apparent with reference to the following detailed description and accompanying drawings.